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Multiple Mosfet Question

Just want to double check my understanding on something.

You can use multiple n- channel Mosfets in a circuit as long as you don't have them in series (and so have one floating when the other turns on the power) and can have p-channel and N-channel in series, is that right?

Would there be any problems with the above?

The N-Channel FETs are fine as they are, I've spent part of this week dealing with much larger arrays of them so that's fine.

The P-Channel looks fine and I can't immediately see a problem but I'm sure SSGT will be along in a moment to point out some arcane issue I've missed. Very Happy

Yeah, as long as the source pin of the FET is always connected to the... er... source (battery/source negative for n-channel and battery/source positive for p-channel) you shouldn't go too far wrong.

Circuits in parallel act, for the most part, independently of each other - things switching on/off in one parallel branch generally won't affect things switching on/off in the other.

Now for the arcane issue (although, to be fair, it shouldn't affect the circuit above). Razz

It's not just N-FETs in series with N-FETs, you should also avoid putting P-FETs in series with P-FETs for the same reason. There are some circumstances where it's acceptable, and others where it probably isn't but you can get away with it anyway, but as you've pointed out the source of one FET will effectively be floating when the other is switched off - FETs effectively work by comparing the voltage at the gate pin to the voltage at the source pin so if the source pin is floating, and therefore has an undetermined voltage, the FET itself will be in an undetermined state (i.e. it's unknown whether it's on/off/somewhere in between). This in of itself isn't necessarily a massive issue in a lot cases (if the second FET is off it will stop current flowing through the first) but what can be a problem is that, because the voltage at a floating pin is undetermined, it's possible for it to exceed VGS(max) (max gate-source voltage - around 20V for most FETs or only 16V for logic-level FETs) and damage the FET. You can put resistors in parallel with each individual FET to "bias" them, and effectively make sure none of the connections are floating (you can work out the voltage between each of the resistors since they form a potential divider), but if you don't run sets of N or P FETs in series you shouldn't have to worry about that. You don't generally need to do this for a P-FET and an N-FET in series (even though the two drain pins will effectively be floating) since VDS(max) (max drain-source voltage) is normally in the region of 100V (at least for TO220 Power FETs) - if you do exceed this voltage most FETs, as long as they are "avalanche rated" and the current/energy dissipated doesn't exceed said avalanche ratings, will dissipate the additional voltage through it's intrinsic "body diode" (a by-product of how the FET is manufactured that is, effectively, a built-in zener diode) rather than being damaged.

Thanks both!

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